Grow a silicon crystal, decode nanometers, compare CPUs and GPUs, open an HBM package, map the global supply chain, follow public money, and read chip export controls without calling every license a ban.
The company on an AI accelerator's label rarely makes every part of it. Follow the silicon, memory, packaging, and manufacturing tools to see where the real dependencies lie.
The cleanest version of the story says NVIDIA or AMD designed a GPU, TSMC printed it, a cloud bought it, and an AI model ran.
The useful version asks what "it" means at every step.
The product may be legally owned in Delaware, designed across California and Israel, fabricated in Taiwan, paired with Korean or American-designed memory made in Asia, joined on an advanced packaging line, mounted into a system by another manufacturer, authorized for export by one government, financed by another, billed to a contract manufacturer's headquarters, and finally installed in a data center whose country is not disclosed.
This is the Chips layer of the AMICE stack: Applications, Models, Infrastructure, Chips, and Energy. The semiconductor atlases retain their September 4, 2026 snapshot, including older records with their original dates. The prose and further reading were reviewed on September 17, 2026. Every interactive fact opens its source. A headquarters is not a fab. An announced fab is not operational capacity. A license is not a ban. An authorization is not a shipment.
Anthropic's hardware history includes more than a proposed custom chip. Google identified TPU v5e serving Claude in November 2023. Anthropic later described securing TPU and GPU clusters while preparing Claude Opus 3. AWS now publishes an Anthropic account of Trainium2 training and serving Claude.
Those deployments sit alongside the April report about Anthropic exploring its own chip design and August reporting on MatX discussions and an expanded silicon team. Development discussions do not establish a finished Anthropic accelerator.
The September 18 documentation review below includes other models' training systems, serving deployments, cloud regions, and electricity records. A missing request-level assignment should lead to the evidence we do have, with its dates and limits attached.
204 additional sources reviewed September 18, 2026. Each record names the workload or geography it supports. Training records describe training; availability and development plans have their own labels.
Your location can suggest a region to research. Endpoint configuration, residency rules, capacity, and cross-region routing determine where a request can run. Nearby data centers are not evidence of your application's serving location.
204 of 204 sources · showing 1-20
Process node
A vendor-defined technology generation—not one literal transistor measurement.
Wafer capacity
Input throughput. It cannot be converted to sellable AI chips without product mix, die area, yield, and packaging.
Memory bandwidth
Peak or sustained data movement, with an explicit per-stack, per-chip, per-package, or per-system boundary.
Commercial state
Authorization, MOU, order, shipment, installation, and operation are different facts.
Chip discussions collapse incompatible units with remarkable ease. A process node is compared as if it were a ruler. Wafer starts are converted into GPUs without die size or yield. HBM bandwidth is quoted without saying whether it describes one stack or a whole accelerator. A country is said to have "bought chips" when the public document only authorizes an export.
The first discipline is simple: preserve the unit, denominator, status, date, and evidence boundary.
The material is silicon, the semiconducting element. Silicone is a different material, a family of rubber-like polymers used in sealants and implants.
Selected silica-rich material is reduced and purified through several industries before it becomes electronic-grade polycrystalline silicon. The manufacturing chain should not jump from a photograph of sand to a finished GPU. Quartz used to make a fused-quartz crystal-growth crucible is also not automatically the source of the silicon atoms inside the wafer.
For the common Czochralski method, a wafer maker melts polysilicon in a high-purity quartz crucible at roughly 1,420°C, adds tiny amounts of dopant, touches a seed crystal to the melt, and slowly pulls and rotates it. The result is a single-crystal cylinder commonly 300 millimeters across and more than a meter long. The ingot is ground, sliced, flattened, etched, mirror-polished, cleaned, and inspected before a foundry patterns a transistor.
A 12-stage physical relay
Focus or click a stage. The path begins with silicon—not silicone—and fans out into design, lithography, memory, packaging, systems, and finally a powered data center.
Wafer makers · physical change
Polysilicon melts in a high-purity quartz crucible. A seed crystal is dipped into the melt, then slowly pulled and rotated to grow a cylindrical monocrystalline ingot.
In plain language: The crystal is grown, not stamped out. A common 300 mm ingot is wider than a dinner plate and can be more than a meter long.
Analogy: Growing an enormous, atomically aligned rock candy—except a misplaced impurity can ruin electrical behavior.
Possible failures
Temperature, rotation, pull speed, dopants, oxygen, and defects must be controlled across a very large crystal.
Geography boundary
Wafer makers operate globally; high-purity quartz for crucibles is its own concentrated upstream dependency.
The journey is not a one-company assembly line. Design happens before masks. Logic fabrication and memory fabrication fan out. Good compute dies and good HBM stacks rejoin through advanced packaging. Packaging and testing can become the bottleneck even while front-end wafer capacity grows.
A label such as "made in America," "made in Taiwan," or "a Korean chip" usually needs another noun. Does it mean the architecture, mask, compute die, memory die, interposer, substrate, package, board, final test, or data-center installation?
A wafer does not pass through one lithography machine and emerge as a processor. The fab repeats a loop:
Lithography supplies spatial instructions. Deposition adds. Etch and polishing remove. Implantation and heat change materials. Metrology closes the feedback loop. A defect discovered after weeks of processing can destroy a large die or push it into a lower performance bin.
ASML's manufacturing explainer describes thousands of steps and more than three months from design to production. Those are useful orders of magnitude, not a public recipe for a named GPU. Exact masks, rework, cycle time, equipment, chemicals, defect density, yield, and capacity allocation are usually confidential.
One terminology trap deserves its own warning. BEOL inside a wafer fab means the metal interconnect layers above the transistors. The semiconductor industry also calls assembly, packaging, and test after wafer fabrication the back end. Those are different stages.
Decades ago, process-node names tracked a physical feature more closely. Modern names such as TSMC N2, Samsung SF2, and Intel 18A identify technology generations. They do not promise a universal two-nanometer or eighteen-ångström component, nor do they guarantee proportional performance across vendors.
EUV adds more numbers that sound similar. Its light has a wavelength of 13.5 nanometers. ASML advertises an eight-nanometer optical-resolution capability for High-NA systems. Neither number is an "8 nm process node," and a lithography system still needs masks, resist chemistry, deposition, etch, overlay, metrology, yield learning, and hundreds of other tools.
The nanometer decoder
Process node
Vendor-defined technology generation: TSMC N2, Samsung SF2, Intel 18A.
Light wavelength
EUV uses 13.5 nm light; ArF DUV uses 193 nm light.
Optical resolution
A relationship among wavelength, numerical aperture, and process factor.
Physical dimensions
Gate length, pitches, wire widths, SRAM cell area—and many other different numbers.
Wavelength λ
13.5nm
Numerical aperture
0.33
Illustrative CD
16.4nm
critical dimension ≈ k₁ × wavelength ÷ numerical aperture
This teaching calculation uses k₁ = 0.4. It illustrates optics, not a foundry process claim. Used for selected critical layers in leading processes; the light path runs through reflective optics in vacuum.
Never convert this optical result into a process-node name.
A smaller node can bring density, power, or performance gains, but cross-vendor labels are not proportional rulers. Compare physical pitches, density method, architecture, voltage, power, yield, cost per good die, and production maturity.
A smaller generation can improve density, power, or performance. It can allow more transistors in an area, reduce some capacitances, introduce new transistor structures, change wiring, or add backside power. But speed also depends on architecture, voltage, frequency, memory, interconnect, package, cooling, software, workload, and yield.
A serious comparison asks for contacted gate pitch, metal pitch and layer, SRAM cell area, density methodology, device architecture, standard-cell library, voltage, power, die area, production maturity, and cost per good die. Vendor percentages retain the vendor's baseline; they are not interchangeable benchmarks.
A CPU is built to move a small number of sophisticated instruction streams through branchy, changing work with low latency. A GPU devotes far more of its area and bandwidth to applying similar numerical operations across enormous arrays. Neural-network training and inference contain enough regular matrix work to keep many parallel lanes busy.
That does not make a GPU a universally better CPU.
The CPU still boots the machine, runs the operating system, prepares data, handles network and storage, executes branch-heavy code, and schedules accelerator work. A custom ASIC such as a TPU or Trainium can be even more efficient when the owner controls a high-volume workload and software stack. An FPGA can rewire its data path after manufacture and can suit specialized low-latency or changing pipelines.
Why GPUs—and why not always GPUs?
An AI server uses CPUs and accelerators together. The meaningful question is not “which chip is best?” but “which architecture keeps this workload moving with acceptable cost, latency, programmability, and energy?”
Thousands of hardware threads can apply similar operations across large arrays of numbers.
Analogy: A huge brigade that is fastest when many cooks perform the same operation in parallel.
Good fit
Tradeoff
AI role: Neural networks spend much of their time in dense, parallel numerical operations, making GPU throughput and an established software ecosystem unusually valuable.
GPUs began in graphics, but their throughput model now serves scientific simulation, databases and analytics, video, image processing, machine learning, and generative AI. Other chips remain essential: CPUs, networking switches, optical DSPs, storage controllers, power-management ICs, security processors, image sensors, analog converters, automotive controllers, RF devices, FPGAs, and microcontrollers.
An "older" process node is not obsolete. High voltage, analog behavior, embedded memory, reliability, qualification, cost, and available capacity can make a mature process the correct technology.
The arithmetic units cannot calculate until their operands arrive. Performance is bounded by whichever resource runs out first: compute throughput, memory bandwidth, memory capacity, latency, network bandwidth, power, or cooling.
High Bandwidth Memory stacks multiple DRAM dies vertically and connects them through silicon vias. The stacks sit beside the accelerator logic on an interposer or other dense package wiring. This short, extremely wide interface moves far more data than a narrow path to distant conventional memory.
Capacity answers "does the model data fit?" Bandwidth answers "how quickly can it move?" Access efficiency and latency answer "how much of that advertised bandwidth does the workload use?"
The memory wall
Capacity decides what fits. Bandwidth decides how fast data can arrive. Latency and access pattern decide how efficiently the hardware uses that bandwidth. HBM improves the first two; it does not erase the third.
Illustrative model size
Weights-only estimate
140GB
70B × 16 bits ÷ 8
1 × 192 GB
Minimum MI300X accelerator count by advertised HBM capacity alone, before any overhead or sharding constraint.
6 × 24 GB
Equivalent capacity in Micron’s 24 GB HBM3E stack example—not a proposed package or supplier allocation.
Weights only—not deployment memory.
This omits activations, KV cache, temporary workspaces, allocator fragmentation, runtime, redundancy, and communication buffers. Training also needs gradients and optimizer state. Quantization quality varies. Common illustrative training/inference storage precision; an actual model can mix formats.
The calculator intentionally stops at model weights. A real inference deployment needs KV cache, activations, workspaces, runtime memory, communication buffers, redundancy, and sharding overhead. Training adds gradients and optimizer state. A lower-bit representation can reduce memory and accelerate supported work, but it can also change model quality and is rarely applied uniformly.
HBM is also its own supply chain. Each memory stack needs DRAM design, wafer fabrication, through-silicon vias, wafer thinning, die test, bonding, a base or control die, stack qualification, and final integration beside the logic. A defect in one component can waste value already added elsewhere.
NVIDIA's performance guide describes the distinction through arithmetic intensity: how much calculation a workload performs for each byte it moves. Work with little reuse can run out of memory bandwidth before it runs out of arithmetic capacity. Bigger peak FLOPS alone will not fix that.
This is why an accelerator comparison needs the workload as well as the specification sheet. Batching can reuse weights across requests, but it also changes memory needs and waiting time. A chip that wins a large-batch throughput test need not deliver the quickest answer to a single user.
Advanced packaging connects compute chiplets, I/O dies, HBM stacks, interposers or bridges, an organic substrate, power delivery, and cooling interfaces within one accelerator package.
TSMC's CoWoS is one commercial family of 2.5D packaging. Other systems use redistribution layers, embedded bridges, or stacked-die approaches. The package must carry huge currents and data rates while staying flat, cool, testable, and manufacturable. Larger packages increase warpage, bonding, substrate, and yield challenges.
A simplified compound-yield equation might multiply the yield of every compute die, memory stack, interposer, substrate, assembly step, and final test. That is useful for intuition and wrong as a production forecast: failures can be correlated, known-good-die testing screens components, redundancy repairs some memory, binning recovers lower-performing products, rework changes outcomes, and yields improve over time.
Count qualified accelerators delivered into working systems. Rectangles drawn on a wafer still need to survive fabrication, packaging, and testing.
The global map below separates headquarters, front-end fabs, memory and packaging, equipment and materials, and policy centers. It does not draw seductive arcs between separately reported locations.
I haven't drawn a default route from NVIDIA through Taiwan and Korea to a data center. NVIDIA's filing can name foundry, memory, packaging, and assembly partners at company scope without mapping one Blackwell revision to one fab, HBM supplier, packaging line, board plant, customer, or deployment site. A line would look more certain than the evidence.
A geography of roles, not inferred routes
The map is representative, not a complete facility census. It deliberately draws no supply arcs: separate disclosures about a headquarters, fab, material district, or policy authority do not prove a particular chip moved between them.
Front-end fabs · mixed
Hsinchu, Taiwan · approximate region coordinates
Multiple wafer fabs and advanced-node expansion, including N2 production disclosed across Hsinchu and Kaohsiung.
Evidence boundary
TSMC discloses site capabilities at portfolio level; this point does not allocate a named NVIDIA, AMD, Apple, or cloud chip to one fab.
Accessible evidence table · 22 places
The visible concentration is still profound. TSMC remains the central advanced-foundry and packaging player. ASML is the sole commercial source of EUV lithography systems. HBM comes from a small group of memory manufacturers. High-purity quartz, photoresists, gases, masks, deposition, etch, inspection, substrates, and testing each have their own concentration and qualification cycles.
Moving one fab does not reproduce the ecosystem. New capacity needs utilities, ultra-pure water, chemicals, masks, spare parts, field-service engineers, process recipes, packaging, test, customers willing to qualify output, and years of yield learning. Geographic diversification can reduce some risks while creating transition, cost, and duplicate-qualification risks.
Google can own Gemini, TPU design, the compiler, Google Cloud, and much of its data-center fleet. It still depends on physical fabrication, memory, packaging, utility infrastructure, construction, and thousands of suppliers. Google Cloud also sells NVIDIA systems.
Microsoft designs Maia and operates Azure while buying and deploying third-party accelerators. Amazon designs Trainium and operates AWS while maintaining a broad GPU portfolio. Meta designs MTIA for internal workloads while buying enormous GPU fleets. Apple controls device silicon, on-device models, and the Private Cloud Compute software trust boundary, yet in 2026 disclosed an extension onto attested Google Cloud infrastructure using NVIDIA hardware. xAI controls Grok and Colossus operations while its disclosed compute platform depends on NVIDIA and the manufacturing chain beneath it.
Vertical integration has an edge
Select a company. “Controls” refers to the named role, not legal ownership of every supplier below it. Custom-chip design is not foundry ownership; a data center is not a power plant; a cloud service can still depend on a competitor’s accelerators.
Deep control of accelerator architecture, systems, networking, and software; external dependence for physical manufacture.
Accelerator and system design
owns / controlsDesigns GPU, CPU, networking, board, rack, and CUDA platform components; Vera Rubin ramped into full production in May 2026 with shipments set for fall 2026, and the Groq 3 LPX inference accelerator uses LPU technology under license from Groq, Inc.
Logic fabrication
external dependencyFabless; names TSMC and Samsung among foundry suppliers.
HBM
external dependencyNames SK hynix, Micron, and Samsung among memory suppliers at company level.
Packaging and assembly
external dependencyDepends on foundry packaging and external manufacturing partners; exact per-SKU allocation can remain private.
End deployment
contracts / buysClouds, model companies, enterprises, and system partners buy and operate the hardware; AWS’s August 2026 plan for 2 million additional Blackwell Ultra, Rubin, and Rubin Ultra GPUs in 2027–2028 is a deployment plan, not installed capacity.
Implication: NVIDIA can set the platform direction without owning the fabs, HBM factories, every packaging line, or the data centers that operate its systems.
Vertical integration changes bargaining power, economics, privacy, optimization, and outage boundaries. It never means "owns everything below the logo."
NVIDIA is the inverse kind of power. It can shape accelerator architecture, systems, networking, and the software ecosystem while remaining fabless. Its foundry, memory, package, assembly, cloud, and energy relationships make it dominant while dependent on those suppliers.
There is no clean public global database of AI-chip purchases by final country.
Customs categories are broad. A system integrator may import a server rather than a loose accelerator. A contract manufacturer can appear as the direct customer. A sovereign project may subsidize access through a privately operated cloud rather than own every chip. Companies disclose orders, commitments, or authorizations without quantities, values, final destinations, or installation status.
NVIDIA's fiscal 2026 geography makes the problem concrete. It reported $42.345 billion of company-wide revenue assigned to Taiwan-headquartered direct customers, but estimated that 76% of Data Center revenue in that Taiwan bucket related to end customers in the United States and Europe. AMD reports a different basis: customer billing location. Neither table is a map of physical deployment or AI-only purchases.
Who pays? First choose the accounting boundary
The controls below do not aggregate currencies or unlike instruments. Every headline retains whether it is a grant ceiling, loan, program envelope, registered fund capital, planned private investment, regulatory authorization, or operating system.
United States · finalized
USD 6.6billion
final direct awardDirect funding tied to construction and production milestones in Arizona.
“Up to” amount; final award does not mean the full amount was immediately disbursed.
United States · available
USD 5billion
available loanLoan financing available under the finalized incentive agreement.
Debt financing is not a grant and should not be added to direct funding as though the instruments were equivalent.
United States · finalized
USD 7.865billion
final direct awardArizona, New Mexico, Ohio, and Oregon projects.
Up-to award with milestone-based disbursements across multiple sites and activities.
United States · finalized
USD 4.745billion
final direct awardTexas semiconductor ecosystem expansion.
Up-to direct funding; completion and operation occur on later milestones.
United States · finalized
USD 6.165billion
final direct awardMemory projects in Idaho and New York.
Up-to award across long-horizon projects; not present HBM production volume.
United States · finalized
USD 0.407billion
final direct awardAdvanced packaging and test facility in Arizona.
Up-to award for a planned facility, not current package output.
European Union · active program
EUR 43billion
program envelopePublic investment ambition intended to mobilize additional private investment across the semiconductor ecosystem.
Multi-instrument policy envelope, not a single award or amount already spent.
China · registered
CNY 344billion
registered capitalState-backed semiconductor investment fund.
Registered capital and bank commitments are not equivalent to money already deployed into factories.
South Korea · planned
KRW 622trillion
planned private investmentPrivate investment plan through 2047 spanning existing and new fabs.
Long-horizon private plan, not a public subsidy or completed capital expenditure.
South Korea · active program
KRW 26trillion
support packageFinancing, infrastructure, tax, and ecosystem support measures.
Package combines different policy instruments and is not a single cash grant.
Japan · finalized
JPY 732billion
subsidy ceilingOriginal support budget ceiling associated with the second Kumamoto fab plan.
The original support ceiling was approved; METI said treatment of the revised 3 nm plan and any additional support was still under examination.
Japan · active program
JPY 72.5billion
subsidy ceilingFive approved compute-resource projects, including procurement of accelerators and cloud infrastructure.
Demand-side compute subsidy ceiling, not a domestic chip-fab award.
Public industrial policy is also incomparable without instrument type. A final direct-award ceiling is not an immediate disbursement. An available loan is not a grant. A 25% tax credit is not an appropriated check. Registered fund capital is not money already invested in a fab. A program envelope can combine national, regional, public, and expected private money. Planned private investment through 2047 is not current government spending.
The geopolitical contest therefore happens through at least five ledgers:
Those ledgers influence one another. They should not be summed into one scoreboard.
"Ban" is often the wrong legal state.
The United States controls specified advanced-computing chips, HBM, manufacturing equipment, software, end users, and end uses through detailed rules. Under the January 2026 BIS policy, qualifying H200, MI325X, and similar exports to China are subject to case-by-case license review and security conditions. That is a dated U.S. licensing policy, not proof of approval, shipment, or permission to import at the destination. A license can be granted and still produce no shipment.
The Netherlands requires authorization for specified advanced semiconductor-manufacturing equipment. Japan added equipment categories to an all-region export-control system with destination-specific licensing treatment. Neither measure is accurately summarized as "the country banned all chip-tool exports to China."
China's gallium- and germanium-related items have remained subject to a global export-license regime since 2023. Additional U.S.-specific restrictions were suspended for a fixed period ending November 27, 2026. The suspension did not erase the underlying global license requirement.
The U.S. AI Diffusion Rule's three-tier world map is another warning. BIS announced its rescission in May 2025. A polished old map can remain visually persuasive after its legal framework disappears.
The “ban” decoder
Rules attach to items, performance, software, end users, end uses, destinations, funding agreements, and effective dates. Country coloring alone cannot decide whether a transaction is legal.
Qualifying applications are reviewed case by case under the revised policy. Approval is conditional, not automatic.
It is not: Neither a blanket authorization nor a blanket prohibition on all advanced accelerators.
CHIPS Act guardrails are different again. A recipient of U.S. manufacturing incentives can accept restrictions on specified expansion or technology-sharing in foreign countries of concern. That contractual funding condition is not identical to an export license or a general rule for companies that never took an award.
For any proposed shipment, a lawyer still needs the exact item classification, performance thresholds, origin and foreign-direct-product rules, end user, end use, destination, license exception, effective date, and named-entity status. This page teaches the vocabulary; it is not a legal determination.
You do not need to memorize semiconductor process integration to see the consequences.
The public story often ends at a brand and a process label. The reporting begins at the missing allocation.
Which HBM vendors are qualified for each accelerator revision? Who fabricates the HBM4 base die? Which packaging line joins it to which logic die? Who bears the loss if one component fails after bonding? Is a capacity number wafer starts, known-good dies, finished packages, servers, or megawatts? How much of a headline subsidy is disbursed? Which license applications are approved, denied, returned, or withdrawn? Is a shipment installed? Is an installed cluster energized and useful?
Reporter mode
Reviewed Sep 4, 2026. This evidence model separates company headquarters, physical production, public finance, buyer-location proxies, and legal controls. A point on the map is not proof that a chip, dollar, or shipment followed a route between points.
10 reporting leads
01Which foundry site, process revision, package line, and HBM supplier actually serve each accelerator generation?
Architecture announcements often name a process family but omit fab, batch, package, yield, and memory allocation. Those unknowns determine geographic concentration and ramp risk.
First documents: supplier and customer 10-Ks · earnings-call transcripts · customs records · local permits · equipment installation disclosures
02Is wafer supply or advanced packaging the binding constraint for the next accelerator ramp?
More front-end wafers do not become deployable systems without interposers, substrates, HBM stacks, test, power delivery, and cooling hardware.
First documents: foundry capacity guidance · OSAT filings · substrate supplier disclosures · HBM qualification statements
03How much of each headline subsidy has been obligated, disbursed, clawed back, or delayed—and against which milestone?
An “up to” final award, an available loan, a tax credit, registered fund capital, and planned private investment are different financial states.
First documents: award terms · agency disbursement reports · recipient cash-flow statements · inspector-general reports · state incentive agreements
04Who is the economic buyer: a cloud, sovereign fund, model company, reseller, system integrator, or end customer?
Customer-headquarters revenue can make Taiwan look like final demand even when a contract manufacturer is purchasing for U.S. or European end customers.
First documents: vendor concentration notes · purchase commitments · cloud capital-expenditure disclosures · importer-of-record data
05How many export-license applications were approved, denied, returned, or withdrawn for each controlled product and destination?
The legal label “license required” does not reveal the real flow unless decisions, conditions, time-to-decision, and product substitutions are known.
First documents: BIS annual reports · FOIA requests · company risk disclosures · customs classifications · end-user certificates
06Are companies, contracts, or policy briefs still relying on the rescinded AI Diffusion Rule’s country tiers?
A visually memorable but obsolete map can keep shaping negotiations after its legal framework has been withdrawn.
First documents: contract compliance schedules · procurement rules · cloud regional restrictions · current EAR citations
07Can a supplier trace semiconductor-grade polysilicon, crucible quartz, gases, photoresists, substrates, and specialty metals to processor lot and country?
National mineral shares describe broad markets. They do not prove the origin of one wafer or package, and several enabling materials follow different routes.
First documents: supplier declarations · bill-of-materials audits · mine and refinery certificates · customs records · quality-lot traceability
08What happens before the November 27, 2026 expiration of China’s U.S.-specific materials-control suspension?
The time-limited suspension sits on top of a continuing global licensing system; procurement teams may be exposed to a sharp policy transition.
First documents: MOFCOM notices · license data · inventory disclosures · refiner contracts · U.S.–China negotiation documents
09What is the good-die yield after logic fabrication, HBM stacking, and package integration—not just wafer starts?
Published wafer capacity can overstate sellable accelerator output when a large package requires many individually good components.
First documents: supplier yield commentary · warranty reserves · binning disclosures · package test data · customer qualification timelines
10How many shipped accelerators are installed, energized, networked, accepted, and running useful workloads?
Shipments and purchase commitments can run ahead of substation energization, cooling commissioning, networking, software maturity, and utilization.
First documents: data-center commissioning records · utility energization dockets · cluster acceptance tests · utilization metrics · cloud capacity disclosures
64 primary or authoritative sources
The ledger is downloadable because a defining page should produce new questions, not only consume them. The stable method is to keep company, facility, product, die, package, policy, financial instrument, commercial state, date, and source separate until the evidence actually connects them.
These reading notes were checked on September 17, 2026. The interactive source ledgers retain their separately dated records.
ASML: six semiconductor manufacturing steps. A manufacturer's illustrated process guide. Helpful for mechanisms, not evidence of a particular GPU's factory route.
ASML: lithography principles. An explanation of optical pattern projection and the limits of wavelength as a process-node comparison.
NVIDIA: GPU performance background. Use its compute-versus-bandwidth reasoning to interrogate accelerator performance claims.